/*
 * File   : top_bench.v
 * Date   : 20171106
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module top_bench();

// CLK
reg axi_clk;
initial
begin
    axi_clk = 0;
    forever #25 axi_clk = !axi_clk;
end

// RST
reg axi_rstn;
initial
begin
    axi_rstn = 0;
    #1000 axi_rstn = 1;
end


// MAIN
reg phy_giga_mode;
reg phy_link_up;
initial                                                
begin                                             
    $display("Testbench running!");
	
	top_bench.phy_giga_mode = 1'b1;
	top_bench.dut.design_1_i.MiniMAC_1Ge_AXI_v1_0_0.inst.MiniMAC_1Ge_AXI_v1_0_S00_AXI_inst.slv_reg0[1:0] = 2'b10;
	top_bench.phy_link_up   = 1'b0;
	top_bench.dut.design_1_i.MiniMAC_1Ge_AXI_v1_0_0.inst.MiniMAC_1Ge_AXI_v1_0_S00_AXI_inst.slv_reg0[1:0] = 2'b10;
	#2000;
	top_bench.phy_link_up   = 1'b1;
    top_bench.dut.design_1_i.MiniMAC_1Ge_AXI_v1_0_0.inst.MiniMAC_1Ge_AXI_v1_0_S00_AXI_inst.slv_reg0[1:0] = 2'b11;
    
    @(top_bench.dut.design_1_i.axi_traffic_gen_0.done);
    #1000;
    $finish;
end

// PHY RGMII: signal naming from DUT point of view
wire       RxClk;
wire       RxDv;
wire [3:0] RxData;
wire       TxClk;
wire       TxEn;
wire [3:0] TxData;
phy_rgmii_bfm bfm_rgmii (
    .RxClk  (RxClk),
    .RxDv   (RxDv),
    .RxData (RxData),
    .TxClk  (TxClk),
    .TxEn   (TxEn),
    .TxData (TxData)
);
//// RGMII loopback for BFM
//assign {TxClk, TxEn, TxData} = {RxClk, RxDv, RxData};

design_1_wrapper dut (
    .USER_RGMII_rd    ( RxData ),
    .USER_RGMII_rx_ctl( RxDv   ),
    .USER_RGMII_rxc   ( RxClk  ),
    .USER_RGMII_td    ( TxData ),
    .USER_RGMII_tx_ctl( TxEn   ),
    .USER_RGMII_txc   ( TxClk  ),
    
    .in_axi_aclk   ( axi_clk       ),
    .in_axi_aresetn( axi_rstn      )
);

endmodule

